1. Field
Exemplary embodiments of the present invention relate to setting information storage circuits for storing setting information for various settings within an integrated circuit chip.
2. Description of the Related Art
An integrated circuit chip requires various settings for a normal operation after the chip is fabricated. For example, only when settings for voltage levels used in an integrated circuit chip and settings for delay values of a delay circuit included in the integrated circuit chip are correctly performed, the integrated circuit chip may operate in an optimal environment. Furthermore, a variety of environments necessary for a test are set, and the test for an integrated circuit chip is performed. As described above, most of integrated circuit chips include a variety of setting circuits for setting operation mode, the voltage levels, and delay values.
FIG. 1 is a diagram illustrating a setting circuit included within a conventional integrated circuit chip.
Referring to FIG. 1, the integrated circuit chip includes a selection code transfer bus 101, a setting data transfer bus 102, a set signal transfer line 103, a reset signal transfer line 104, a plurality of decoders 110_0 to 110_N, a plurality of register sets 120_0 to 120_N, and a plurality of internal circuits 130_0 to 130_N.
The selection code transfer bus 101 transfers external selection codes SEL<0:A> received from a source other than the integrated circuit chip. The selection codes SEL<0:A> designate that external setting data DATA<0:B> received from a source other than the integrated circuit chip to be stored in one of the plurality of register sets 120_0 to 120_N. The setting data transfer bus 102 transfers the external setting data DATA<0:B>. The setting data DATA<0:B> is stored in a register set that is selected in response to the selection codes SEL<0:A>. The set signal transfer line 103 transfers an external set signal SET received from a source other than the integrated circuit chip. Furthermore, the reset signal transfer line 104 transfers an external reset signal RST received from a source other than the integrated circuit chip. The set signal SET includes timing information that designates a time at which setting data starts being inputted to a register set selected in response to the selection codes SEL<0:A>. The reset signal RST includes timing information that designates a time at which the setting data DATA<0:B> starts being inputted to a register set selected in response to the selection codes SEL<0:A>.
The decoders 110_0 to 110_N generate input enable signals EN_0 to EN_N in response to the selection codes SEL<0:A>, the set signal SET, and the reset signal RST. If the selection codes SEL<0:A> has a corresponding value to one of the decoders 110_0 to 110_N, one of the decoders 110_0 to 110 N enables the respective input enable signals EN_0 to EN_N in response to the enabling of the set signal SET and disable the respective input enable signals EN_0 to EN_N in response to the enabling of the reset signal RST. For example, assuming that the number of decoders 110_0 to 110_N is 8 (that is, N=7) and the selection codes SEL<0:A> have 3 bits (that is, A=2), if the selection codes SEL<0:2> have a value of ‘000’, the decoder 110_0 enables the input enable signal EN_0 in response to the enabling of the set signal SET and disables the input enable signal EN_0 in response to the enabling of the reset signal RST. Furthermore, if the selection codes SEL<0:2> have a value of ‘010’, the decoder 110_2 enables the input enable signal EN_2 in response to the enabling of the set signal SET and disables the input enable signal EN_2 in response to the enabling of the reset signal RST.
The register sets 120_0 to 120_N receive and store the setting data DATA<0:B> loaded onto the setting data transfer bus 102 while the respective input enable signals EN_0 to EN_N are enabled. For example, while the input enable signal EN_1 is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus 102, is stored in the register set 120_1. While the input enable signal EN_3 is enabled, the setting data DATA<0:B>, which is loaded onto the setting data transfer bus 102, is stored in the register set 120_3.
The internal circuits 130_0 to 130_N perform setting necessary for respective operations by using setting data stored in respective register sets. For example, if the internal circuit 130_0 is a circuit for setting the operation mode of the integrated circuit chip, the internal circuit 130_0 may set the operation mode of the integrated circuit chip in mode A or mode B by using setting data stored in the register set 120_0. Furthermore, if the internal circuit 130_1 is a circuit for generating an internal voltage used in the integrated circuit chip, the internal circuit 130_1 may set the level of the internal voltage by using setting data stored in the register set 120_1. Furthermore, if the internal circuit 130_2 is a delay circuit for delaying a specific signal, the internal circuit 130_2 may set a delay value by using setting data stored in the register set 120_2.
The setting method used in the above-described integrated circuit chip is performed in such a manner that a setting item is selected in response to the selection codes SEL<0:A>, and setting information DATA<0:B> is inputted to the selected setting item. Accordingly, the number of items that may be set varies depending on the number of bits of the selection codes SEL<0:A>. In order to increase the number of items that may be set in this setting method, the number of bits of the selection codes SEL<0:A> has to be increased. If the number of bits of the selection codes SEL<0:A> is increased, however, there are concerns in that an area of the selection code transfer bus 101 must be increased and the design of the decoders 110_0 to 110_N must be changed. In particular, in the case of an integrated circuit chip in which the number of bits of the selection codes SEL<0:A> is determined in accordance with standards, such as JEDEC and IEEE, there is a concern in that an increase in the number of bits of the selection codes SEL<0:A> may violate the standards. Accordingly, there is a need for technology that can increase the number of items that may be set without increasing the number of bits of the selection codes SEL<0:A> and changing the design of the decoder 110_0 to 110_N.